Veri cation of Bounded Delay Asynchronous Circuits with Timed Traces

In this paper, we extend the veriication method based on the failure semantics of process algebra and the resulting trace theory by Dill et al. for bounded delay asynchronous circuits. We deene a timed conformance relation between trace structures which allows to express both safety and responsiveness properties. In our approach, bounded delay circuits as well as their real-time properties are modelled by time Petri nets. We give an explicit state-exploration algorithm to determine whether an implementation conforms to a speciication. Since for IO-connict free speciications the conformance relation is transitive, this algorithm can be used for hierarchical veriication of large asynchronous circuits. We describe the implementation of our method and give some experimental results which demonstrate its eeciency.